The following description of the background of the invention is provided simply as an aid in understanding the invention and is not admitted to describe or constitute prior art to the invention.
Semiconductor devices are commonly tested using specialized processing equipment. The processing equipment may be used to identify defective products and other various characteristics related to the performance of such devices. In most cases, the processing equipment possesses mechanisms for handling devices under test. In order to ensure accurate testing, handling mechanisms must be able to correctly align the device under test with various other testing tools and equipment. Correct alignment of the devices is essential for efficient testing.
Various systems are used to position and align devices for testing, sorting and other functions. Generally, alignment is achieved using a mechanical alignment system. However, mechanical alignment is only accurate within certain manufacturing ranges and is not ideal for precise alignment operations. Further, modern devices with finer pitches are driving the need for optically assisted alignment, or “vision alignment,” as an alternative to mechanical alignment.
Conventional vision alignment systems used for aligning devices in a two dimensional coordinate system use the three axis motion control of an actuator set to align one device to a contactor in x, y and theta (rotation angle) directions.
Accordingly, each device is aligned independently by a set of actuators. However, for a test handler used to simultaneously test an increased number of devices, there is typically no space to put more actuator sets to align each device individually. Additionally, increasing the number of actuators also dramatically increases the system cost.
Devices and methods that address these issues are described in, for example, U.S. Pat. No. 7,506,451, U.S. Pat. No. 8,106,349, and U.S. Pat. No. 7,842,912, all of which are assigned to the Assignee of the present application and are incorporated by reference in their entireties. The devices and methods described in these patents are particularly advantageous for use with single sided IC device testing.